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| ? motorola inc., 1994 motorola technical data semiconductor the DSP56156 is a general-purpose mpu-style digital signal processor (dsp). on a single semi- conductor chip, the DSP56156 comprises a very efficient 16-bit digital signal processing core, pro- gram and data memories, a number of peripherals, and system support circuitry. unique features of the DSP56156 include a built-in sigma-delta (2y) codec and phase-locked loop (pll). this com- bination of features makes the DSP56156 a cost-effective, high-performance solution for many dsp applications, especially speech coding, digital communications, and cellular base stations. the central processing unit of the DSP56156 is the dsp56100 core processor. like all dsp56100- based dsps, the DSP56156 consists of three execution units operating in parallel, allowing up to six operations to be performed during each instruction cycle. this parallelism greatly increases the effective processing speed of the DSP56156. the mpu-style programming model and instruction set allow straightforward generation of efficient, compact code. the basic architectures and devel- opment tools of motorola's 16-bit, 24-bit, and 32-bit dsps are so similar that understanding how to design and program one greatly reduces the time needed to learn the others. on-chip emulation (once tm port) circuitry provides convenient and inexpensive debug facil- ities normally available only through expensive external hardware. development costs are re- duced and in-field testing is greatly simplified using the once tm port. figure 1 illustrates the DSP56156 in detail. figure 1 DSP56156 block diagram specifications and information herein are subject to change without notice. once is a trademark of motorola, inc. data 16 control 9 address 16 data alu 16 x 16 + 40 > 40-bit mac two 40-bit accumulators pll clock gen. gdb pdb xdb internal data bus switch external data bus switch bus control pab xab1 xab2 address generation unit external address bus switch irq 2 16-bit bus 16-bit 56100 dsp core program address generator program decode controller interrupt control program control unit sigma- delta codec 4 3 once? port 16-bit timer/ event counter sync. serial (ssi) or i/o host interface (hi) or i/o 5 15 2 (boot) sync. serial (ssi) or i/o 5 7 data memory 2048 16 ram program memory * 2048 16 ram 64 16 rom * 12 k x 16 rom replaces the program ram on the DSP56156rom advance information 16-bit digital signal processor DSP56156 order this document by DSP56156/d rev 1 DSP56156rom
2 DSP56156 data sheet motorola introduction DSP56156 features digital signal processing core ? efficient, object code compatible, 16-bit 56100-family dsp engine up to 30 million instructions per second (mips) C 33 ns instruction cycle at 60 mhz up to 180 million operations per second (mops) at 60 mhz highly parallel instruction set with unique dsp addressing modes two 40-bit accumulators including extension byte parallel 16 16-bit multiply-accumulate in 1 instruction cycle (2 clock cycles) double precision 32 32-bit multiply with 72-bit result in 6 instruction cycles least mean square (lms) adaptive loop filter in 2 instructions 40-bit addition/subtraction in 1 instruction cycle fractional and integer arithmetic with support for multiprecision arithmetic hardware support for block-floating point fft hardware-nested do loops including infinite loops zero-overhead fast interrupts (2 instruction cycles) three 16-bit internal data buses and three 16-bit internal address buses for maximum information transfer on-chip memory ? on-chip harvard architecture permitting simultaneous accesses to program and memories ? 2048 16-bit on-chip program ram and 64 16-bit bootstrap rom (or 12 k 16-bit on-chip program rom on the DSP56156rom) ? 2048 16-bit on-chip data ram ? external memory expansion with 16-bit address and data buses ? bootstrap loading from external data bus, host interface, or synchronous serial interface peripheral and support circuits ? byte-wide host interface (hi) with direct memory access support ? two synchronous serial interfaces (ssi) to communicate with codecs and synchronous serial devices built in -law and a-law compression/expansion up to 32 software-selectable time slots in network mode ? 16-bit timer/event counter also generates and measures digital waveforms ? on-chip sigma-delta voice band codec: sampling clock rates between 100 khz and 3 mhz four software-programmable decimation/interpolation ratios internal voltage reference ( 2 / 5 of positive power supply) no external components required DSP56156 features motorola DSP56156 data sheet 3 introduction ? on-chip peripheral registers memory mapped in data memory space ? double buffered peripherals ? up to 27 general purpose i/o pins ? two external interrupt request pins ? on-chip emulation (once?) port for unobtrusive, processor speed-independent debugging ? software-programmable, phase-locked loop-based (pll) frequency synthesizer for the core clock miscellaneous features ? power-saving wait and stop modes ? fully static, hcmos design for operating frequencies from 40 or 60 mhz down to dc ? 112-pin ceramic quad flat pack (cqfp) surface-mount package; 20 20 3 mm ? 112-pin plastic thin quad flat pack (tqfp) surface-mount package; 20 20 1.5 mm ? 5 v power supply product documentation this data sheet plus the two manuals listed in table 1 are required for a complete DSP56156 description and are necessary to properly design with the part. documentation is available from a local motorola distributor, a semiconductor sales office, or through a motorola litera- ture distribution center. table 1 DSP56156 documentation topic description order number dsp56100 family manual detailed description of the 56000- family architecture and the 16-bit core processor and instruction set dsp56100famum/ad DSP56156 users manual detailed description of memory, peripherals, and interfaces DSP56156um/ad DSP56156 data sheet pin and package descriptions, and electrical and timing specifications DSP56156/d DSP56156 features documentation 4 DSP56156 data sheet motorola introduction related documentation table 2 lists additional documentation relevant to the DSP56156. data sheet contents this data sheet contains: ? signal definitions and pin locations ? electrical specifications and timings ? package descriptions ? design considerations ? ordering information table 2 related motorola documentation topic description order number dsp family brochure overview of all dsp product families br1105/d development tools product brief. includes ordering information dsptoolsp/d fractional and integer arithmetic application report. includes code apr3/d fast fourier transforms (ffts) application report. comprehensive fft algorithms and code for dsp56001, DSP56156, and dsp96002 apr4/d g.722 audio processing application report. theory and code using sb-adpcm apr404/d dr. bub bulletin board flyer. motorolas electronic bulletin board where free dsp software is available br297/d third party compendium brochures from companies selling hardware and software that supports motorola dsps dsp3rdptypak/d university support program flyer. motorolas program that sup- ports universities in dsp research and education br382/d documentation data sheet contents motorola DSP56156 data sheet 5 introduction pin groupings the DSP56156 is available in a 112-pin ceramic quad flat pack (cqfp) and a 112-pin plastic thin quad flat pack (tqfp). the input and output signals are organized into the functional groups indicated in table 3. figure 2 illustrates the chips pin functions. note: overbars are used throughout this document to indicate a signal which is at ground voltage (typi- cally a ttl logic low v il or v ol ) when the function is logically true. these signals are, likewise, at v cc voltage (typically a ttl logic high v ih or v oh ) when the function is logically false. table 3 functional pin groupings functional group number of pins address 16 data bus 16 bus control 9 host interface (hi) 15 synchronous serial interfaces (ssi) 10 timer interface 2 interrupt and mode control 4 phase-locked loop (pll) and clock 3 on-chip emulation (once tm port) 4 on-chip codec 7 power (v cc )10 ground (gnd) 16 to t a l 11 2 pin groupings 6 DSP56156 data sheet motorola introduction figure 2 DSP56156 pin functions * these pins have an alternate function of general purpose input/output. h0-h7* ha0-ha2* hr/w * hen * hreq * hack * interrupt/ mode control DSP56156 host interface (hi) on-chip emulator (once ? ) port std0* srd0* sck0* sc00-sc10* std1* srd1* sck1* sc01-sc11* mic aux spkm bias vref vdiv v cc gnd spkp moda/irqa modb/irqb modc reset extal clko sxfc a0-a15 d0-d15 bs ps/ds wr rd r/w ta br bg bb dsi/os0 dsck/os1 dso dr clock and phase-locked loop (pll) external bus on-chip codec two synchronous serial interfaces (ssi) 112 pins timer/event counter tin* tout* pin functions pin descriptions motorola DSP56156 data sheet 7 pin descriptions address and data bus a0-a15 (address bus) three-state, active high outputs. a0-a15 change in t0 and specify the address for external pro- gram and data memory accesses. if there is no external bus activity, a0-a15 remain at their previous values. a0-a15 are three-stated during hardware reset. d0-d15 (data bus) three-state, active high, bidirectional input/outputs. read data is sampled on the trailing edge of t2, while write data output is enabled by the leading edge of t2 and three-stated at the leading edge of t0. if there is no external bus activity, d0-d15 are three-stated. d0-d15 are also three- stated during hardware reset. bus control ps/ds (program/data memory select) three-state, active low output. this out- put is asserted only when external data memory is referenced. ps/ds timing is the same for the a0-a15 address lines. ps/ds is high for program memory ac- cess and is low for data memory access. if the external bus is not used during an in- struction cycle (t0, t1, t2, t3), ps/ds goes high in t0. ps/ds is in the high imped- ance state during hardware reset. r/w (read/write) three-state, active low output. timing is the same as the address lines, providing an early write signal. r/w (which changes in t0) is high for a read access and is low for a write access. if the external bus is not used during an instruction cycle (t0, t1, t2, t3), r/w goes high in t0. r/w is three-stated during hardware reset. wr (write enable) three-state, active low output. this output is asserted dur- ing external memory write cycles. when wr is asserted in t1, the data bus pins d0-d15 become outputs and the dsp puts data on the bus during the leading edge of t2. when wr is deasserted in t3, the external data has been latched inside the external device. when wr is assert- ed, it qualifies the a0-a15 and ps/ds pins. wr can be connected directly to the we pin of a static ram. wr is three- stated during hardware reset or when the dsp is not bus master. rd (read enable) three-state, active low output. this output is asserted during external memory read cycles. when rd is asserted in late t0/early t1, the data bus pins d0-d15 become in- puts and an external device is enabled onto the data bus. when rd is deas- serted in t3, the external data is latched inside the dsp. when rd is asserted, it qualifies the a0-a15 and ps/ds pins. rd can be connected directly to the oe pin of a static ram or rom. rd is three-stated during hardware reset or when the dsp is not bus master. bs (bus strobe) three-state, active low output. asserted at the start of a bus cycle (during t0) and deasserted at the end of the bus cycle (during t2). this pin provides an early bus start signal which can be used as address latch and as an early bus end signal which can be used by an external bus controller. bs is three-stated during hardware reset. address and data bus bus control 8 DSP56156 data sheet motorola pin descriptions ta (transfer acknowledge) active low input. if there is no external bus ac- tivity, the ta input is ignored by the dsp. when there is external bus cycle activity, ta can be used to insert wait states in the external bus cycle. ta is sampled on the leading edge of the clock. any number of wait states from 1 to infinity may be inserted by using ta . if ta is sampled high on the leading edge of the clock beginning the bus cy- cle, the bus cycle will end 2t after the ta has been sampled low on a leading edge of the clock; if the bus control reg- ister (bcr) value does not program more wait states. the number of wait states is determined by the ta input or by the bus control register (bcr), whichever is longer. ta is still sampled during the leading edge of the clock when wait states are controlled by the bcr value. in that case, ta will have to be sampled low during the leading edge of the last period of the bus cycle pro- grammed by the bcr (2t before the end of the bus cycle programmed by the bcr) in order not to add any wait states. ta should always be deasserted during t3 to be sampled high by the leading edge of t0. if ta is sampled low (assert- ed) at the leading edge of the t0 begin- ning the bus cycle, and if no wait states are specified in the bcr register, zero wait states will be inserted in the exter- nal bus cycle, regardless the status of ta during the leading edge of t2. br (bus request) active low output when in master mode, active low in- put when in slave mode. after power- on reset, this pin is an input (slave mode). in this mode, the bus request br allows another device such as a pro- cessor or dma controller to become the master of the dsp external data bus d0-d15 and external address bus a0-a15. the dsp asserts bg a few t states after the br input is asserted. the dsp bus controller releases control of the external data bus d0-d15, ad- dress bus a0-a15 and bus control pins ps/ds , rd , wr , and r/w at the earli- est time possible consistent with prop- er synchronization. these pins are then placed in the high impedance state and bus control t0 t1 t2 t3 t0 t1 t2 tw t2 t3 t0 t1 t2 t3 t0 t1 t2 tw t2 tw t2 t3 t0 t1 t2 tw t2 tw t2 tw t2 t3 t0 t1 t2 tw t2 tw t2 t3 t0 t1 t2 clko ta bs clko ta bs figure 3 ta controlled accesses pin descriptions motorola DSP56156 data sheet 9 the bb pin is deasserted. the dsp con- tinues executing instructions only if in- ternal program and data memory resources are accessed. if the dsp re- quests the external bus while br input pin is asserted, the dsp bus controller inserts wait states until the external bus becomes available (br and bb deas- serted). note that interrupts are not serviced when a dsp instruction is waiting for the bus controller. note also that br is prevented from inter- rupting the execution of a read/ modi- fy/write instruction. if the master bit in the omr register is set, this pin becomes an output (master mode). in this mode, the dsp is not the external bus master and has to assert br to request the bus mastership. the dsp bus controller will insert wait states until bg input is asserted and will then begin normal bus accesses af- ter the rising of the clock which sam- pled bb high. the br output signal will remain asserted until the dsp no long- er needs the bus. in this mode, the re- quest hold bit (rh) of the bus control register (bcr) allows br to be asserted under software control. during external accesses caused by an instruction executed out of external pro- gram memory, br remains asserted low for consecutive external x memory ac- cesses and continues toggling for con- secutive external p memory accesses unless the request hold bit (rh) is set inside the bus control register (bcr). in the master mode, br can also be used for non arbitration purpose: if bg is always asserted, br is asserted in t0 of every external bus access. it can then be used as a chip select to turn a exter- nal memory device off and on between internal and external bus accesses. br timing is in that case similar to a0-a15, r/w and ps/ds ; it is asserted and deasserted during t0. bg (bus grant) active low input when in master mode, active low output when in slave mode. output after power on reset if the slave is selected, this pin is asserted to acknowledge an external bus request. it indicates that the dsp will release control of the ex- ternal address bus a0-a15, data bus d0-d15 and bus control pins when bb is deasserted. the bg output is assert- ed in response to a br input. when the bg output is asserted and bb is deas- serted, the external address bus a0-a15, data bus d0-d15 and bus control pins are in the high impedance state. bg as- sertion may occur in the middle of an instruction which requires more than one external bus cycle for execution. note that bg assertion will not occur during indivisible read-modify-write instructions (bfset, bfclr, bfchg). when br is deasserted, the bg output is deasserted and the dsp regains con- trol of the external address bus, data bus, and bus control pins when the bb pin is sampled high. this pin becomes an input if the master bit in the omr register is set (master mode). it is asserted by an external pro- cessor when the dsp may become the bus master. the dsp can start normal external memory access after the bb pin has been deasserted by the previous bus master. when bg is deasserted, the dsp will release the bus as soon as the current transfer is completed. the state of bg may be tested by testing the bs bit in the bus control register. bg is ig- nored during hardware reset. bus control 10 DSP56156 data sheet motorola pin descriptions bb (bus busy) active low input when not bus master, active low output when bus master. this pin is asserted by the dsp when it becomes the bus master and it performs an external ac- cess. it is deasserted when the dsp re- leases bus mastership. bb becomes an input when the dsp is no longer the bus master. interrupt and mode control moda/irqa (mode select a/external in- terrupt request a) input. this in- put has two functions: ? to select the initial chip operating mode and, ? to allow an external device to request a dsp interrupt after internal syn- chronization. moda is read and internally latched in the dsp when the processor exits the reset state. moda and modb select the initial chip operating mode. several clock cycles after leaving the reset state, the moda pin changes to the external interrupt request irqa . the chip oper- ating mode can be changed by soft- ware after reset. the irqa input is a synchronized ex- ternal interrupt request which indi- cates that an external device is requesting service. it may be pro- grammed to be level sensitive or nega- tive edge triggered. if level sensitive triggering is selected, an external pull up resistor is required for wired-or operation. if the processor is in the stop standby state and irqa is asserted, the processor will exit the stop state. modb/irqb (mode select b/external in- terrupt request b) input. this in- put has two functions: ? to select the initial chip operating mode and, ? to allow an external device to request a dsp interrupt after internal syn- chronization. modb is read and internally latched in the dsp when the processor exits the reset state. moda and modb select the initial chip operating mode. several clock cycles after leaving the reset state, the modb pin changes to the external interrupt request irqb . after reset, the chip operating mode can be changed by software. the irqb input is an external interrupt request which indicates that an exter- nal device is requesting service. it may be programmed to be level sensitive or negative edge triggered. if level sensi- tive triggering is selected, an external pull up resistor is required for wired- or operation. modc (mode select c) input. this input selects the initial bus operating mode. when tied high, the external bus is pro- grammed in the master mode (br out- put and bg input) and when tied low the bus is programmed in the slave mode (br input and bg output). modc is read and internally latched in the dsp when the processor exits the reset state. after reset , the bus operat- ing mode can be changed by software by writing the mc bit of the omr register. reset (reset) input. this input is a direct hardware reset of the processor. when reset is asserted, the dsp is initialized and placed in the reset state. a schmitt interrupt and mode control bus control pin descriptions motorola DSP56156 data sheet 11 trigger input is used for noise immunity. when the reset pin is deasserted, the ini- tial chip operating mode is latched from the moda and modb pins, and the ini- tial bus operating mode is latched from the modc pin. the internal reset signal should be deasserted synchronized with the internal clocks. host interface h0-h7 (host data bus) bidirectional. this bidirectional data bus is used to transfer data between the host processor and the dsp. this bus is an input unless enabled by a host processor read. h0-h7 may be programmed as port b general purpose parallel i/o pins called pb0-pb7 when the host interface (hi) is not being used. ha0-ha2 (host address 0-2) input*. these inputs provide the address selection for each hi register and are stable when hen is asserted. ha0-ha2 may be programmed as port b general pur- pose parallel i/o pins called pb8-pb10 when the hi is not being used. hr/w (host read/write) input*. this in- put selects the direction of data transfer for each host processor access. if hr/w is high and hen is asserted, h0-h7 are outputs and dsp data is transferred to the host processor. if hr/w is low and hen is asserted, h0-h7 are inputs and host data is transferred to the dsp. when hen is asserted, hr/w is stable. hr/w may be programmed as a gen- eral purpose i/o pin called pb11 when the hi is not being used. hen (host enable) input*. this input en- ables a data transfer on the host data bus. when hen is asserted and hr/w is high, h0-h7 becomes an output and dsp data may be latched by the host processor. when hen is asserted and hr/w is low, h0-h7 is an input and host data is latched inside the dsp when hen is deasserted. normally a chip select signal derived from host ad- dress decoding and an enable clock is connected to the host enable. hen may be programmed as a general pur- pose i/o pin called pb12 when the hi is not being used. hreq (host request) output*. this open- drain output signal is used by the hi to request service from the host proces- sor. hreq may be connected to an in- terrupt request pin of a host processor, a transfer request of a dma controller, or a control input of external circuitry. hreq is asserted when an enabled re- quest occurs in the hi. hreq is deas- serted when the enabled request is cleared or masked, dma hack is as- serted, or the dsp is reset. hreq may be programmed as a general purpose i/o pin (not open-drain) called pb13 when the hi is not being used. hack (host acknowledge) input*. this input has two functions: ? to provide a host acknowledge signal for dma transfers and, ? to control handshaking and to pro- vide a host interrupt acknowledge compatible with mc68000 family processors. if programmed as a host acknowledge signal, hack may be used as a data strobe for hi dma data transfers. if pro- grammed as an mc68000 host interrupt host interface * these pins can be bidirectional when programmed as general purpose i/o. interrupt and mode control 12 DSP56156 data sheet motorola pin descriptions acknowledge, hack enables the hi interrupt vector register (ivr) onto the host data bus h0-h7 if the host re- quest hreq output is asserted. in this case, all other hi control pins are ig- nored and the hi state is not affected. hack may be programmed as a gen- eral purpose i/o pin called pb14 when the hi is not being used. 16-bit timer tin (timer input) input*. this input re- ceives external pulses to be counted by the on-chip 16-bit timer when external clocking is selected. the pulses are in- ternally synchronized to the dsp core internal clock. tin may be pro- grammed as a general purpose i/o pin called pc10 when the external event function is not being used. tout (timer output) output*. this out- put generates pulses or toggles on a timer overflow event or a compare event. tout may be programmed as a general purpose i/o pin called pc11 when disabled by the timer out enable bits (to2-to0). synchronous serial interfaces (ssi) std0-1 (ssi0-1 transmit data) output*. these output pins transmit serial data from the ssi0-1 transmit shift register. std0 and std1 may be programmed as a general purpose i/o pin called pc0 and pc5, respectively, when the std function is not being used. srd0-1 (ssi0-1 receive data) input*. these input pins receive serial data and transfer the data to the ssi0-1 receive shift register. srd0 and srd1 may be programmed as a general purpose i/o pin called pc1 and pc6, respectively, when the srd function is not being used. sck0-1 (ssi0-1 serial clock) bidirection- al. these bidirectional pins provide the serial bit rate clock for the ssi0-1 inter- face. sck0 and sck1 may be pro- grammed as a general purpose i/o pin called pc2 and pc7, respectively, when the ssi0-1 interfaces are not be- ing used. sc10-11 (ssi0-1 serial control 1) bidirec- tional. these bidirectional pins are used by the ssi0-1 serial interface as frame sync i/o or flag i/o. sc10 and sc11 may be programmed as a general purpose i/o pin called pc3 and pc8, respectively, when the ssi0-1 are not using these pins. sc00-01 (ssi0-1 serial control 0) bidirec- tional. these bidirectional pins are used by the ssi0-1 serial interface as frame sync i/o or flag i/o. sc00 and sc01 may be programmed as a general purpose i/o pin called pc4 and pc9, respectively, when the ssi0-1 are not using these pins. 16-bit timer ssi * these pins can be bidirectional when programmed as general purpose i/o. pin descriptions motorola DSP56156 data sheet 13 on-chip emulation (once tm port) dsi/os0 (debug serial input/chip status 0) bidirectional. the dsi/os0 pin, when an input, is the pin through which seri- al data or commands are provided to the once port controller. the data re- ceived on the dsi pin will be recog- nized only when the dsp has entered the debug mode of operation. data must have valid ttl logic levels before the serial clock falling edge. data is al- ways shifted into the once serial port most significant bit (msb) first. when the dsp is not in the debug mode, the dsi/ os0 pin provides information about the chip status if it is an output and used in conjunction with the os1 pin. dsck/os1 (debug serial clock/chip status 1) bidirectional. the dsck/os1 pin, when an input, is the pin through which the serial clock is supplied to the once port. the serial clock provides pulses required to shift data into and out of the once serial port. data is clocked into the once port on the fall- ing edge and is clocked out of the once serial port on the rising edge. if the dsck/os1 pin is an output and used in conjunction with the os0 pin, it provides information about the chip status when the dsp is not in the debug mode. dso (debug serial) output. the debug serial output provides the data con- tained in one of the once port control- ler registers as specified by the last command received from the command controller. when idle, this pin is high. when the requested data is available, the dso line will be asserted (negative true logic) for four t cycles (one instruction cycle) to indicate that the serial shift reg- ister is ready to receive clocks in order to deliver the data. when the chip enters the debug mode due to an external de- bug request (dr ), an internal software debug request (debug), a hardware breakpoint occurrence or a trace/step occurrence, this line will be asserted for three t cycles to indicate that the chip has entered the debug mode and is wait- ing for commands. data is always shift- ed out the once serial port with the most significant bit first. dr (debug request) input. the debug request input provides a means of en- tering the debug mode of operation. this pin, when asserted, will cause the dsp to finish the current instruction be- ing executed, enter the debug mode, and wait for commands to be entered from the debug serial input line. on-chip codec aux (auxiliary) input . this pin is select- ed as the analog input to the a/d con- verter when the ins bit is set in the codec control register cocr. this pin should be left floating when the codec is not used. bias (bias current) input . this input is used to determine the bias current for the analog circuitry. connecting a re- sistor between bias and gnda will program the current bias generator. this pin should be left floating when the codec is not used. mic (microphone) input . this pin is se- lected as the analog input to the a/d converter when the ins bit is cleared in once on-chip codec 14 DSP56156 data sheet motorola pin descriptions the codec control register cocr. this pin should be left floating when the co- dec is not used. spkp (speaker plus) output . this pin is the positive analog output from the on- chip d/a converter. this pin should be left floating when the codec is not used. spkm (speaker minus) output . this pin is the negative analog output from the on-chip d/a converter. this pin should be left floating when the codec is not used. vref (voltage reference) output . this pin is the op-amp buffer output in the reference voltage generator. it has a value of ( 2 / 5 )v cca . this pin should al- ways be connected to the gnda through two capacitors, even when the codec is not used. vdiv (voltage division) output . this output pin is also the output to the on- chip op-amp buffer in the reference voltage generator. it is connected to a resistor divider network located within the codec block which provides a volt- age equal to ( 2 / 5 )v cca . this pin should be connected to the gnd via a capacitor when the codec is used and should be left floating when the codec is not used. power, ground, and clock v cc (power) power pins gnd (ground) ground pins v ccs (synthesizer power) this pin sup- plies a quiet power source to the phase- locked loop (pll) to provide greater frequency stability. gnds (synthesizer ground) this pin sup- plies a quiet ground source to the pll to provide greater frequency stability. v cca (analog power) this pin is the posi- tive analog supply input. it should be con- nected to v cc when the codec is not used. gnda (analog ground) this pin is the an- alog ground return. it should be con- nected to digital gnd when the codec is not used. extal (external clock) input. this input should be driven by an external clock or by an external oscillator. after being squared, the input frequency can be used as the dsp core internal clock. in that case, it is divided by two to produce a four phase instruction cycle clock, the minimum instruction time being two in- put clock periods. this input frequency is also used, after division, as input clock for the on-chip codec and the on- chip pll. clko (clock output) output. this pin outputs a buffered clock signal. by pro- gramming two bits (cs1-cs0) inside the pll control register (plcr), the user can select between outputting a squared version of the signal applied to extal, a squared version of the signal applied to extal divided by 2, and a delayed version of the dsp core master clock. the clock frequency on this pin can be disabled by setting the clockout disable bit (cd; bit 7) of the operating mode register (omr). when disabled, the pin can be left floating. sxfc (external filter capacitor) this pin adds an external capacitor to the pll filter circuit. a low leakage capacitor should be connected between and lo- cated very close to sxfc and v ccs . power, ground, and clock on-chip codec electrical characteristics and timing motorola DSP56156 data sheet 15 electrical characteristics and timing caution : exceeding maximum electrical ratings will permanently damage or disable the chip, or impair the chips long term reliability. the DSP56156 is fabricated in high density hcmos with ttl compatible inputs and cmos compatible outputs. note: this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either gnd or v cc ). table 4 maximum electrical ratings (gnd = 0 vdc) rating symbol value unit supply voltage v cc -0.3 to +7.0 v all input voltages v in gnd - 0.5 to v cc + 0.5 v current drain per pin excluding v cc and gnd i 10 ma storage temperature t stg -55 to +150 c table 5 operating conditions supply voltage v cc junction temperature t j ( c) min max min max 4.5 5.5 -40 115 table 6 thermal characteristics of cqfp and tqfp packages thermal resistance characteristics symbol value rating cqfp tqfp junction to ambient q ja 40 49 c/w junction to case (estimated) q jc 78 c/w electrical characteristics and timing 16 DSP56156 data sheet motorola analog i/o characteristics (v cc a = 5.0 v dc 10%, t j = -40 to +125 c) the analog i/o characteristics of this device are listed in table 7. for additional information regarding the use of analog signals, see design considerations at the end of this document. table 7 analog i/o characteristics characteristic min typ max unit input impedance on mic and aux (see note 1) 46 78 1400 k w input capacitance on mic and aux 10pf peak input voltage on the mic/aux input for full scale linearity (0.14 dbm0): 6 db - mgs1 - 0 = 00 (see note 2) 0 db - mgs1 - 0 = 01 6 db - mgs1 - 0 = 10 17 db - mgs1 - 0 = 11 1.414 0.707 354 100 vp vp mvp mvp internal input gain variation; g = -6 db, 0 db, 6 db or 17 db (0.83 db variation due to 10% variation on v cc ): g - 0.83 g g + 0.83 db vref output voltage 1.8 2 2.2 v vref output current 1 ma dc offset between spkp and spkm 100 mv allowable differential load capacitance on spkp and spkm (with 1 k w in series) 0 0.05 f allowable single-ended load capacitance on spkp or spkm (with 0.5 k w in series) 0 (see note 3) 100 0.1 f maximum single-ended signal output level 1 vp maximum differential signal output level 2 vp single-ended load resistance 500 w differential load resistance 1 k w resistance bias 10 (see note 4) k w internal output volume control variation vc = -20, -15, -10, -5, 0, 6, 12, 18, 24, 30, 35 db ( 0.83 db variation due to 10% variation on v cc ) vc - 0.83 vc vc + 0.83 db notes: 1. minimum value reached for a codec clock of 3 mhz, typical for 2 mhz and maximum for 100 khz 2. 0 dbm0 corresponds to 3.14 db below the input saturation level 3. ac coupling is necessary in single-ended mode when the load resistor is not tied to vref 4. 10% analog i/o characteristics electrical characteristics and timing motorola DSP56156 data sheet 17 a/d and d/a performance (v cca = 5.0 v dc 10%, t j = -40 to +125 c) the a/d and d/a performance of the codec section are given in table 8 with an example presented in figure 4. notes: 1. 0 db gain on the a/d and d/a; codec clock at 1.538 mhz with 128 decimation/interpolation ratio and tested at 1502 hz 2. 0 dbm0 corresponds to -3.14 db below the input saturation level figure 4 example: s/n and s/n+t performance for the a/d section table 8 a/d and d/a performance of codec characteristic level min typ (see note 1) max unit analog to digital section signal to noise plus distortion ratio (s/n+t) 0 dbm0 (see note 2) 55 65 db -50 dbm0 15 20 db digital to analog section signal to noise plus distortion ratio (s/n+t) 0 db 55 65 db -50 db 15 20 db s in db 0 10 20 30 40 50 60 70 80 s/n s/n+t signal in db 13 codec (12+1)*4 2 mhz 1 mhz pll 52 mhz cocr=$e400 pll codec (12+1)x4 13 6.5 13 mhz a/d and d/a performance electrical characteristics and timing 18 DSP56156 data sheet motorola other on-chip codec characteristics (v cca = 5.0 v dc 10%, t j = -40 to +125 c, c l = 50 pf + 1 ttl load) the analog i/o characteristics of this device are shown in table 9. table 9 analog i/o characteristics of on-chip codec characteristic min typ max unit codec master clock 0.1 2.048 3 mhz codec sampling rate 78 16000 37000 hz a/d section group delay 0.2msec d/a section group delay 0.2 msec other on-chip codec characteristics dc electrical characteristics and timing motorola DSP56156 data sheet 19 dc electrical characteristics (gnd = 0 v dc) (v cc = 5.0 v dc 10%, t j = -40 to +125 c, c l = 50 pf + 1 ttl load) the dc electrical characteristics of this device are shown in table 10. notes: 1. when extal is ac coupled, v ihc - v ilc ? 1 v must be true. 2. input capacitance is periodically sampled and not 100% tested in production. table 10 dc electrical characteristics characteristic symbol min typ max unit input high voltage except extal, reset , moda, modb, modc v ih 2.0 v cc v input low voltage except extal, moda, modb, modc v il -0.5 0.8 v input high voltage extal dc coupled extal ac coupled (see note 1) v ihc 70% of v cc 1 v cc v cc v input low voltage extal dc coupled extal ac coupled (see note 1) v ilc -0.5 -0.5 20% of v cc v cc -1 v input high voltage reset v ihr 2.5 v cc v input high voltage moda, modb, modc v ihm 3.5 v cc v input low voltage moda, modb, modc v ilm -0.5 2.0 v input leakage current extal reset , moda, modb, modc, ta , dr , br i in -100 -1 100 1 a a three-state (off-state) input current (@2.4 v/0.5 v) tsi -10 10 a output high voltage (i oh = -10 a) v ohc v cc -0.1 v output high voltage (i oh = -0.4 ma) v oh 2.4 v output low voltage (i ol = 10 a) v olc 0.1v output low voltage (i ol = 3.2 ma r/w i ol = 1.6 ma; open drain hreq i ol = 6.7 ma, txd i ol = 6.7 ma) v ol 0.4v input capacitance (see note 2) c in 10pf ac electrical characteristics and timing 20 DSP56156 data sheet motorola ac electrical characteristics (gnd = 0 v dc) the timing waveforms in the ac electrical characteristics are tested with a v il maximum of 0.5 v and a v ih minimum of 2.4 v for all pins, except extal, reset , moda, modb and modc. these five pins are tested using the input levels set forth in the dc electrical charac- teristics . ac timing specifications which are referenced to a device input signal are measured in production with respect to the 50% point of the respective input signals transition. the DSP56156 output levels are measured with the production test machine v ol and v oh refer- ence levels set at 0.8 v and 2.0 v respectively. clock operation timing the system clock to the DSP56156 must be externally supplied to extal as illustrated in figure 6. notes: 1. rise and fall time may be relaxed to 12 ns maximum if the extal input frequency is less than or equal to 20 mhz. if the extal input frequency is between 20 mhz and 40 mhz, rise and fall time should meet the specified values in the 40 mhz column (4 ns maximum). 2. the duty cycle may be relaxed to 43-57% if the extal input frequency is less than or equal to 20 mhz. if the extal input frequency is between 20 mhz and 40 mhz, the duty cycle should be such that t h and t l meet the specified values in the 40 mhz column (12 ns minimum). 3. t = i cyc / 4 is used in the electrical characteristics. the exact length of each t is affected by the duty cycle of the external clock input. 4. duty cycles and extal widths are measured at the extal input signal midpoint when ac coupled and at v cc /2 when not ac coupled. table 11 clock operation timing num characteristics sym 40 mhz 50 mhz 60 mhz unit min max min max min max 1 frequency of operation (extal) f 0 40 0 50 0 60 mhz 2 instruction cycle time = 2t c i cyc 50 4033ns 3 wait state time = t c = 2t 25 20 16.6 ns 4 extal cycle period t c 25 20 16.6 ns 5 extal rise time (see note 1) 4 3 3 ns 6 extal fall time (see note 1) 4 3 3 ns 7 extal width high 48-52% duty cycle (see notes 2, 3, 4) t h 12 9.6 8 ns 8 extal width low 48%-52% duty cycle (see notes 2, 3, 4) t l 12 9.6 8 ns clock operation timing ac electrical characteristics and timing motorola DSP56156 data sheet 21 figure 5 external clock timing other clock and pll operation timing clock and pll timings are listed in table 12 and the clocking configurations are illustrated in figure 6. figure 6 clocking configurations extal v ihc midpoint 7 8 4 2 5 6 t h t l 90% 10% v ilc table 12 clock and pll timing characteristics min max unit pll output frequency 10 max fosc (see note 1) mhz extal input clock amplitude (see note 2) 1 v cc vpp notes: 1. maximum dsp operating frequency. see table 11. 2. an ac coupling capacitor is required on extal if the levels are out of the normal cmos level range (v ilc >20% of v cc or v ihc <70% of v cc ). extal pll plle=1 plle=0 fosc ed3-ed0 clko ? 2 internal phase ph0 at fosc cs1-cs0 1000 pf gsm sxfc v ccs xfc 0.01 m f gnds 0.1 m f 100 k w ? 1 to ? 16 ? 6.5 codec vco lf pfd yd3-yd0 ? 1 to ? 16 10 nf ? 4 clock operation timing pll ac electrical characteristics and timing 22 DSP56156 data sheet motorola reset, stop, wait, mode select, and interrupt timing (v cc = 5.0 v dc 10%, t j = -40 to +125 c, c l = 50 pf + 1 ttl load) cyc = clock cycle = 1 / 2 instruction cycle = 2 t cycles ws = number of wait states programmed into external bus access using bcr (ws = 0 - 31) table 13 reset, stop, wait, mode select, and interrupt timing num characteristics 40 mhz 50 mhz 60 mhz unit min max min max min max 10 reset assertion to address, data and control signals high impedance 2523 21ns 11 minimum stabilization duration (see note 1) omr bit 6=0 omr bit 6=1 600kt 60t 600kt 60t 600kt 60t ns ns 12 asynchronous reset deassertion to first external address output (see note 7) 16t 18t+20 16t 18t+17 16t 18t+15 ns 13 synchronous reset setup time from reset deassertion to rising edge of clko 7 cyc-4 6 cyc-3 5 cyc-2 ns 14 synchronous reset delay time from clko high to the first external access (see note 7) 16t+3 16t+20 16t+ 3 16t+18 16t+3 16t+16 ns 15 mode select setup time 22 20 18 ns 16 mode select hold time 00 0 ns 17 edge-triggered interrupt request width 13 11 9 ns 18 delay from irqa , irqb assertion to external data memory access out valid - caused by first interrupt instruction fetch - caused by first interrupt instruction execution 11t+4 19t+4 11t+4 19t+4 11t+3 19t+3 ns ns 19 delay from irqa , irqb assertion to general purpose output valid caused by the execution of the first interrupt instruction 22t+5 22t+4 22t+3 ns 20 delay from external data memory address output valid caused by first interrupt instruction execution to inter- rupt request deassertion for level sen- sitive fast interrupts (see note 2) 5t-26 + cyc ws 5t-24 + cyc ws 5t-22 + cyc ws ns reset, stop, wait, mode select, and interrupt timing ac electrical characteristics and timing motorola DSP56156 data sheet 23 (v cc = 5.0 v dc 10%, t j = -40 to +125 c, c l = 50 pf + 1 ttl load) table 13 reset, stop, wait, mode select, and interrupt timing (continued) num characteristics 40 mhz 50 mhz 60 mhz unit min max min max min max 21 delay from general-purpose output valid caused by the execution of the first inter- rupt instruction to irqa , irqb deassertion for level sensitive fast interrupts if 2nd interrupt instruction is: single cycle (see note 2) two cycles cyc - 29 3 cyc - 29 cyc - 27 3 cyc - 27 cyc - 26 3 cyc - 26 ns ns 22 synchronous setup time from irqa , irqb assertion to synchronous falling edge of clko (see notes 5 and 6) 14 cyc-3 13 cyc-2 12 cyc-1 ns 23 falling edge of clko to first interrupt vector address out valid after synchronous recovery from wait state (see notes 3 and 5) 27t+3 27t+20 27t+3 27t+18 27t+3 27t+16 ns 24 irqa width assertion to recover from stop state (see note 4) 15 13 12 ns 25 delay from irqa assertion to fetch of first instruction (exit- ing stop) (see notes 1 and 3) omr bit 6=0 omr bit 6=1 524303t+4 47t+4 524303t+3 47t+3 524303t+3 47t+3 ns ns 28 duration for level sensitive irqa assertion to cause the fetch of first irqa interrupt instruction (exiting stop) (see notes 1 and 3) omr bit 6=0 omr bit 6=1 524303t 47t 524303t 47t 524303t 47t ns ns 29 delay from level sensitive irqa assertion to first inter- rupt vector address out valid (exiting stop) (see notes 1 and 3) omr bit 6=0 omr bit 6=1 524303t+4 47t+4 524303t+3 47t+3 524303t+3 47t+3 ns ns reset, stop, wait, mode select, and interrupt timing ac electrical characteristics and timing 24 DSP56156 data sheet motorola notes: 1. circuit stabilization delay is required during reset when using an external clock in two cases: ? after power-on reset ? when recovering from stop mode 2. when using fast interrupts, irqa or irqb is defined as level-sensitive, then timings 20 and 21 apply to prevent multiple interrupt service. to avoid these timing restrictions, the negative edge-trig- gered mode is recommended when using fast interrupts. 3. the interrupt instruction fetch is visible on the pins only in mode 3. 4. the minimum is specified for the duration of an edge triggered irqa interrupt required to recover from the stop state. this is not the minimum required so that the irqa interrupt is accepted. 5. timing #22 is for all irqx interrupts while timing #23 is only when exiting the wait state. 6. timing #22 triggers off t1 in the normal state and off phi1 when exiting the wait state. 7. the instruction fetch is visible on the pins only in mode 2 and mode 3. figure 7 asynchronous reset timing figure 8 synchronous reset timing reset d0-d15 a0-a15 ps/ds r/w bs 10 11 12 first fetch v ihr clko reset a0-a15 ps/ds bs r/w 14 13 reset, stop, wait, mode select, and interrupt timing ac electrical characteristics and timing motorola DSP56156 data sheet 25 figure 9 operating mode select timing figure 10 external interrupt timing (negative edge-triggered) figure 11 external level-sensitive fast interrupt timing reset moda modb modc v ihr irqa irqb v ihm v ilm v ih v il 16 15 irqa irqb 17 first interrupt instruction execution a0-a15 ps/ds bs r/w irqa irqb 20 18 a) first interrupt instruction execution general purpose i/o pin irqa irqb 19 21 b) general purpose i/o reset, stop, wait, mode select, and interrupt timing ac electrical characteristics and timing 26 DSP56156 data sheet motorola figure 12 synchronous interrupt from wait state timing figure 13 recovery from stop state using asynchronous interrupt timing figure 14 recovery from stop state using irqa interrupt service 22 23 t0, t2 phi0 t1, t3 phi1 clko irqa irqb a0-a15 pd/ds bs r/w instruction fetch first interrupt irqa a0-a15 pd/ds bs r/w 24 25 not irqa interrupt vector first instruction fetch irqa a0-a15 pd/ds bs r/w first irqa interrupt instruction fetch 28 29 reset, stop, wait, mode select, and interrupt timing ac electrical characteristics and timing motorola DSP56156 data sheet 27 table 14 wait and stop timings num characteristics 40 mhz 50 mhz 60 mhz unit min max min max min max 30 dr asserted to clk high (setup time for synchronous recovery from wait state) 10 cyc - 4 9 cyc - 3 8 cyc - 2 ns 31 clk high to dso (ack ) valid (enter debug mode) after syn- chronous recovery from wait state 18 cyc 18 cyc 18 cyc ns 32 dr to dso (ack ) valid (enter debug mode) - after asynchronous recovery from stop state - after asynchronous recovery from wait state 29 cyc 18 cyc 29 cyc 18 cyc 29 cyc 18 cyc ns ns 33 dr assertion width - to recover from wait/stop without entering debug mode - to recover from wait/stop short wake-up and enter debug mode - to recover from stop long wake-up and enter debug mode 12 29 cyc 262157 cyc 10 cyc 11 29 cyc 262157 cyc 10 cyc 10 29 cyc 262157 cyc 10 cyc ns ns ns figure 15 recovery from wait state using dr pin synchronous timing dr (input) dso (output) 33 32 33 reset, stop, wait, mode select, and interrupt timing ac electrical characteristics and timing 28 DSP56156 data sheet motorola figure 16 recovery from wait/stop state using dr pin asynchronous timing capacitance derating the DSP56156 external bus timing specifications are designed and tested at the maximum ca- pacitive load of 50 pf, including stray capacitance. typically, the drive capability of the exter- nal bus pins (a0-a15, d0-d15, ps/ds , rd , bs , wr , r/w ) derates linearly at 1 ns per 12 pf of additional capacitance from 50 pf to 250 pf of loading. port b and c pins derate linearly at 1 ns per 5 pf of additional capacitance from 50 pf to 250 pf of loading. when an internal memory access follows an external memory access, the ps/ds , r/w , rd and wr strobes remain deasserted and a0-a15 do not change from their previous state. clko (output) dr (input) dso (output) 31 t1, t3 30 33 t0, t2 reset, stop, wait, mode select, and interrupt timing capacitance derating ac electrical characteristics and timing motorola DSP56156 data sheet 29 external bus synchronous timing (v cc = 5.0 v dc 10%, t j = -40 to +125 c, c l = 50 pf + 1 ttl load) table 15 lists external bus synchronous timing. figure 17 and illustrate the bus timings with no wait states and two wait states, respectively. table 15 external bus synchronous timing num characteristic 40 mhz 50 mhz 60 mhz unit min max min max min max 34 extal clk in high to clko high 2.4 9 2.4 9 2.4 9 ns 35 clko high to a. a0-a15 valid b. ps/ds , r/w valid, bs , rd asserted 4.7 4.7 12 14 4.7 4.7 12 14 4.7 4.7 12 (see note) 4 ns ns 36 bs width deasserted 18.3 13.4 9.8 ns 37 clko high to wr asserted low t+3.1 t+12.4 t+3.1 t+12.4 t+3.1 t+12.4 ns 38 wr and rd deasserted high to bs asserted low (2 successive bus cycles) 14.3 15.8 11.8 13.3 10.2 11.8 ns 39 ac electrical characteristics and timing 30 DSP56156 data sheet motorola note: during read-modify-write instructions and internal instructions, the address lines do not change state. figure 17 external bus synchronous timing no wait states extal (input) t0 t1 t2 t3 t0 t1 t2 data in 37 35 35 41 43 data out 34 36 40 42 47 48 51 50 46 49 45 47 48 clko (output) a0-a15 ps/ds r/w (see note) bs (output) wr (output) rd (output) ta (input) d0-d15 (output) d0-d15 (input) 41 35 44 external bus synchronous timing ac electrical characteristics and timing motorola DSP56156 data sheet 31 figure 18 external bus synchronous timing C two wait states extal (input) t0 t1 t2 tw t2 tw t2 t3 t0 data in 37 35 41 43 44 data out 34 36 40 42 47 48 51 50 46 49 45 35 47 48 42 41 clko (output) a0-a15, ps/ds , r/w (outputs) bs (output) wr (output) rd (output) ta (input) d0-d15 (output) d0-d15 (input) 35 external bus synchronous timing ac electrical characteristics and timing 32 DSP56156 data sheet motorola external bus asynchronous timing (v cc = 5.0 v dc 10%, t j = -40 to +125 c, c l = 50 pf + 1 ttl load) cyc = clock cycle = 1 / 2 instruction cycle = 2 t cycles ws = number of wait states, determined by bcr register (ws = 0 to 31) wt = ws cyc = 2t ws external bus asynchronous timing ac electrical characteristics and timing motorola DSP56156 data sheet 33 figure 19 external bus asynchronous timing data in 64 59 data out 62 67 68 54 66 69 58 57 63 65 61 55 a0-a15, ps/ds , r/w (see note) 53 60 56 bs wr d0-d15 rd 52 note: during read-modify-write instructions and internal instructions, the address lines do not change state. external bus asynchronous timing ac electrical characteristics and timing 34 DSP56156 data sheet motorola bus arbitration timing slave mode (v cc = 5.0 v dc 10%, t j = -40 to +125 c, c l = 50 pf + 1 ttl load) cyc = clock cycle = 1 / 2 instruction cycle = 2 t cycles ws = number of wait states for external x or p memory, determined by bcr register (ws = 0 to 31) wt = ws cyc=2t ws wx = number of wait states for external x memory, determined by bcr register (ws = 0 to 31) wp = number of wait states for external p memory, determined by bcr register (ws = 0 to 31) notes: 1. with no external access from the DSP56156 2. during external read or write access 3. during external read-modify-write access 4. during stop mode external bus is released and bg is always low 5. during wait mode 6. with external accesses pending by the DSP56156 7. slave mode, when bus is still busy after bus request has been deasserted table 17 slave mode num characteristics 40/50/60 mhz unit min max 70 br input to clko low setup time 0 1 ns 71 delay from br input assertion to (see note 1) bg output assertion (see note 2) (see note 3) (see note 4) (see note 5) 5t+1.9 3t+1.9 5t+1.9 na t+1.9 9t+4.2 6t+wt+4.2 26t+4t x wx +2t x wp+4.2 na 3t+4.2 ns 72 clko high to bg output assertion 1.9 5.2 ns 73 bg output deassertion duration (see note 1) (see note 5) (see note 6) 5t-0.5 2t-0.5 3t-0.5 ns 74 clko high to control bus high impedance 2.7 6.5 ns 75 clko high to bb output deassertion 3.2 7.8 ns 76 clko high to bb input 3.3 8.1 ns 77 br input deassertion to (see note 1) bg output deassertion (see note 5) (see note 7) 4t+2.5 3t+3.2 3t+3.2 9t+6.4 8t+7.8 8t+8.0 ns 78 clko low to bg deassertion (see note 1) clko high to bg deassertion (see note 5) clko high to bg deassertion (see note 7) 2.5 3.2 3.2 6.4 7.8 8.0 ns 79 clko high to bb output active 1.3 3.6 ns 80 clko high to bb output assertion 2.3 5 ns 81 clko high to address and control bus active 1 3 ns 82 clko high to address and control bus valid 2 4.4 ns bus arbitration timing slave mode ac electrical characteristics and timing motorola DSP56156 data sheet 35 figure 20 bus arbitration timing slave mode bus release 72 74 70 71 74 76 75 73 clko (output) br (input) bg (output) bb (i/o) a0-a15 ps/ds r/w d0-d15 bus arbitration timing slave mode ac electrical characteristics and timing 36 DSP56156 data sheet motorola figure 21 bus arbitration timing slave mode bus acquisition 70 78 80 79 77 81 82 clko (output) br (input) bg (output) bb (i/o) a0-a15 ps/ds r/w bus arbitration timing slave mode ac electrical characteristics and timing motorola DSP56156 data sheet 37 bus arbitration timing master mode (v cc = 5.0 v dc 10%, t j = -40 to +125 c, c l = 50 pf + 1 ttl load) figure 22 bus arbitration timing master mode bus acquisition table 18 master mode num characteristic 40 mhz 50 mhz 60 mhz unit min max min max min max 85 clko high to br output assertion clko high to br output deassertion 4.7 12 4.7 12 4.7 12 ns 86 bg input asserted/ deasserted to clko low (setup) 9.2 6.54.5 ns 87 clko low to bg input invalid (hold) 000ns 88 bb input deasserted to clko low (setup) 9.2 6.5 4.5 ns 89 clko low to bb input deasserted (hold) 0 0 0 ns 90 clko high to bb output asserted 4.7 12 4.7 12 4.7 12 ns 86 85 89 88 87 90 81 82 three-state clko (output) br (output) bg (input) bb (i/o) a0-a15 ps/ds r/w bus arbitration timing master mode ac electrical characteristics and timing 38 DSP56156 data sheet motorola figure 23 bus arbitration timing master mode bus release 85 86 87 74 76 75 clko (output) br (output) bg (input) bb (i/o) a0-a15 ps/ds r/w bus arbitration timing master mode ac electrical characteristics and timing motorola DSP56156 data sheet 39 host port timing (v cc = 5.0 v dc 10%, t j = -40 to +125 c, c l = 50 pf + 1 ttl load) t = i cyc / 4 cyc = clock cycle = 1 / 2 instruction cycle= 2 t cycle t hsdl = host synchronization delay time (see note 1) t suh = host processor data setup time active low lines should be pulled up in a manner consistent with the ac and dc specifica- tions. table 19 host port timing num characteristic 40 mhz 50 mhz 60 mhz unit min max min max min max 100 thsdl host synchronous delay (see note 1) t 3tt3t t 3tns 101 hen /hack assertion width ? cvr, icr, isr read ? read ? write (see notes 2, 4) 2t+36 32+t suh 32 2t+33 29+t suh 29 2t+30 26+t suh 26 ns 102 hen /hack deassertion width (see note 2) 31 29 27 ns 103 minimum cycle time between two hen assertion for consecutive cvr, icr, isr reads 4t+36 4t+33 4t+30 ns 104 host data input setup time before hen /hack deassertion 543ns 105 host data input hold time after hen /hack deassertion 765ns 106 hen /hack assertion to output data active from high impedance 000ns 107 hen /hack assertion to output data valid 322926ns 108 hen /hack deassertion to output data high impedance 20 18.5 17 ns 109 output data hold time after hen /hack deassertion 554ns host port timing ac electrical characteristics and timing 40 DSP56156 data sheet motorola notes: 1. host synchronization delay (thsdl) is the time period required for the DSP56156 to sample any external asynchronous input signal, determine whether it is high or low, and synchronize it to the internal clock. 2. see host port considerations . 3. hreq is pulled up by 1 k w. 4. only if two consecutive reads from one of these registers are executed. table 19 host port timing (continued) num characteristic 40 mhz 50 mhz 60 mhz unit min max min max min max 110 hr/w low setup time before hen assertion 6 5 4 ns 111 hr/w low hold time after hen deassertion 6 5 4 ns 112 hr/w high setup time to hen assertion 6 5 4 ns 113 hr/w high hold time after hen /hack deassertion 5 43ns 114 ha0-ha2 setup time before hen assertion 9 7.5 6 ns 115 ha0-ha2 hold time after hen deassertion 8 76ns 116 dma hack assertion to hreq deassertion (see note 3) 52t +37 52t +36 42t +35 ns 117 dma hack deassertion to hreq assertion (see note 3) for dma rxl read for dma txl write for all other cases t hsdl +3t+5 t hsdl +2t+5 5 t hsdl 3t+5 t hsdl +2t+5 5 t hsdl +3t+4 t hsdl +2t+4 4 ns ns ns 118 delay from hen deassertion to hreq assertion for rxl read (see note 3) t hsdl +3t+5 t hsdl +3t+5 t hsdl +3t+4 ns 119 delay from hen deassertion to hreq assertion for txl write (see note 3) t hsdl +2t+5 t hsdl +2t+5 t hsdl +2t+4 ns 120 delay from hen assertion to hreq deassertion for rxl read, txl write (see note 3) 52t +37 52t +36 52t +35 ns host port timing ac electrical characteristics and timing motorola DSP56156 data sheet 41 figure 24 host synchronization delay figure 25 host interrupt vector register (ivr) read external internal 100 100 hreq (output) hack (input) hr/w (input) h0-h7 (output) 102 103 112 113 108 107 106 109 data valid 101 host port timing ac electrical characteristics and timing 42 DSP56156 data sheet motorola figure 26 host read cycle (non-dma mode) figure 27 host write cycle (non-dma mode) hreq (output) hen (input) ha0-ha2 (input) hr/w (input) h0-h7 (output) 118 120 103 101 102 114 115 112 113 107 108 109 rxl read rxh read address valid address valid data valid data valid 106 119 120 101 102 114 115 txl write txh write address valid address valid data valid data valid hreq (output) hen (input) ha0-ha2 (input) hr/w (input) h0-h7 (input) 110 111 104 105 103 host port timing ac electrical characteristics and timing motorola DSP56156 data sheet 43 figure 28 host read cycle (dma mode) figure 29 host write cycle (dma mode) data valid data valid rxl read rxh read hreq (output) hack (input) h0-h7 (output) 101 102 116 117 107 106 108 109 hreq (output) hack (input) h0-h7 (input) 101 102 116 117 104 105 data valid data valid txl write txh write host port timing ac electrical characteristics and timing 44 DSP56156 data sheet motorola synchronous serial interfaces (ssi) timing (v cc = 5.0 v dc 10%, t j = -40 to + 125 c, c l = 50 pf + 1 ttl load) t= i cyc / 4 sck = serial clock pin fst (transmit frame sync) = scx0 pin fsr (receive frame sync) = scx1 pin i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (asynchronous implies that fsr and fst are two different frame syncs) i ck s = internal clock, synchronous mode (synchronous implies that only one frame sync fs is used) bl = bit length wl = word length note: all the timings for the ssi are given for a non-inverted serial clock polarity (sckp=0 in crb) and a non- inverted frame sync (fsi=0 in crb). if the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal sck and/or the frame sync fsr/fst in the tables and in the figures. table 20 synchronous serial interfaces timing num characteristic 40/50/60 mhz case unit min max 130 clock cycle (see note) 100 ns 131 clock high period 45 ns 132 clock low period 45 ns 133 output clock rise/fall time 7 ns 134 sck rising edge to fsr out (bl) high 32 18 x ck i ck a ns 135 sck rising edge to fsr out (bl) low 32 15 x ck i ck a ns 136 sck rising edge to fsr out (wl) high 32 15 x ck i ck a ns 137 sck rising edge to fsr out (wl) low 32 15 x ck i ck a ns 138 data in setup time before sck falling edge 30 40 x ck i ck ns 139 data in hold time after sck falling edge 25 12 x ck i ck ns ssi timing ac electrical characteristics and timing motorola DSP56156 data sheet 45 ssi timing ac electrical characteristics and timing 46 DSP56156 data sheet motorola table 20 synchronous serial interfaces timing (continued) num characteristic 40/50/60mhz case unit min max 140 fsr input (bl) high before sck falling edge 7 15 x ck i ck a ns 141 fsr input (wl) high before sck falling edge 7 15 x ck i ck a ns 142 fsr input hold time after sck falling edge 15 7 x ck i ck a ns 143 flags input setup before sck falling edge 7 15 x ck i ck ns 144 flags input hold time after sck falling edge 15 7 x ck i ck ns 145 sck rising edge to fst out (bl) high 33 15 x ck i ck ns 146 sck rising edge to fst out (bl) low 30 15 x ck i ck ns 147 sck rising edge to fst out (wl) high 30 15 x ck i ck ns 148 sck rising edge to fst out (wl) low 33 15 x ck i ck ns 149 sck rising edge to data out enable from high impedance 30 12 x ck i ck ns 150 sck rising edge to data out valid 30 12 x ck i ck ns 151 sck rising edge to data out high impedance 30 20 x ck i ck ns 152 fst input (bl) setup time before sck falling edge 6 16 x ck i ck ns 153 fst input (wl) to data out enable from high impedance 36 ns 154 fst input (wl) setup time before sck falling edge 8 17 x ck i ck ns 155 fst input hold time after sck falling edge 15 4 x ck i ck ns 156 flag output valid after sck rising edge 32 15 x ck i ck ns ssi timing ac electrical characteristics and timing motorola DSP56156 data sheet 47 figure 30 ssi receiver timing sck (input/output) fsr (bit) out fsr (word) out data in fsr (bit) in fsr (word) in flags in first bit last bit 131 132 133 130 134 135 136 137 138 139 140 142 142 141 143 144 ssi timing ac electrical characteristics and timing 48 DSP56156 data sheet motorola figure 31 ssi transmitter timing note : in the network mode, output flag transitions can occur at the start of each time slot within the frame. in the normal mode, the output flag state is asserted for the entire frame period. 150 151 155 152 153 155 156 first bit last bit (see note) 132 130 133 131 145 146 147 148 149 150 sck (input/output) fst (bit) out fst (word) out data out fst (bit) in fst (word) in flags out 154 timer timing ac electrical characteristics and timing motorola DSP56156 data sheet 49 timer timing (v cc = 5.0 v dc 10%, t j = -40 to +125 c, c l = 50 pf + 1 ttl load) figure 32 timer timing table 21 timer timing num characteristic 40/50/60 mhz unit min max 170 tin valid to clko low (setup time) 6 ns 171 clko low to tin invalid (hold time) 0 ns 172 clko high to tout asserted 3.5 14 ns 173 clko high to tout deasserted 5.1 20.7 ns 174 tin period 8t ns 175 tin high/low period 4t ns 170 172 171 173 clko (output) tin (input) tout (output) once port timing ac electrical characteristics and timing 50 DSP56156 data sheet motorola once tm port timing (v cc = 5.0 v dc 10%, t j = -40 to +125 c, c l = 50 pf + 1 ttl load) notes: 1. 45%-55% duty cycle 2. td = dsck high (timing #183) table 22 once port timing num characteristic 40/50/60 mhz unit min max 180 dsck high to dso valid 37ns 181 dsi valid to dsck low (setup) 5.2 ns 182 dsck low to dsi invalid (hold) 0 ns 183 dsck high (see note 1) 2tc ns 184 dsck low (see note 1) 2tc ns 185 dsck cycle time (see note 1) 4tc ns 186 clko high to os0-os1 valid 14.5 ns 187 clko high to os0-os1 invalid ns 188 last dsck high to os0-os1 (see note 2) last dsck high to ack active (data) (see note 2) last dsck high to ack active (command) (see note 2) 10t+td+14.5 10t+td+13.5 21t+td+13.5 ns 189 dso (ack ) asserted to os0-os1 three-state 0 ns 190 dso (ack ) asserted to first dsck high 3tc ns 191 dso (ack ) width asserted: ? when entering debug mode ? when acknowledging command/data transfer 3t-2 2tc+0.5 3t-5 2tc+3 ns ns 192 last dsck high of read register to first dsck high of next command 6tc ns 193 dsck high to dso invalid (see note 2) td+11.2 ns 194 dr asserted to dso (ack ) asserted 11t+19.5 ns once port timing ac electrical characteristics and timing motorola DSP56156 data sheet 51 figure 33 once port serial clock timing figure 34 once port acknowledge timing figure 35 once port data i/o to status timing dsck (input) 185 183 184 194 ack dr (input) dso (output) 188 (ack ) (os0) (os1) (last) dsck (input) dso (output) dsi (input) 193 180 181 182 (see note) note: three-state, external pull-down resistor once port timing pin-out and package 52 DSP56156 data sheet motorola pin-out and package information figure 39 top view of the DSP56156 112-pin plastic (fc) and ceramic (fe) quad flat packages gnd4 d2 d3 v cc3 d4 d5 gnd5 d6 d7 d8 d9 gnd6 d10 d11 v cc4 d12 d13 gnd7 d14 d15 ta dr v cca spkp spkm gnda vdiv vref orientation mark 1 29 57 85 d1 d0 a15 a14 gnd3 a13 a12 a11 gndq1 v cc2 a10 gnd2 a9 a8 a7 a6 v ccq1 gnd1 a5 a4 v cc1 a3 a2 gnd0 a1 a0 modc modb/irqb note: an overbar indicates the signal is asserted when the voltage = ground (active low). mic aux bias bg v ccq0 br bb v cc5 wr gnd8 rd ps/ds bs r/w dso dsck/os1 dsi/os0 clko gndq0 gnds sxfc v ccs extal sc01/pc9 gnd9 sc11/pc8 sck1/pc7 h7/pb7 (top view) moda/irqa reset std0/pc0 srd0/pc1 sck0/pc2 sc10/pc3 sc00/pc4 tin/pc10 v cc7 tout/pc11 ha0/pb8 gnd10 ha1/pb9 ha2/pb10 hr/w /pb11 hen /pb12 hack /pb14 hreq /pb13 h0/pb0 h1/pb1 std1/pc5 srd1/pc6 h4/pb4 h3/pb3 h2/pb2 v cc6 h5/pb5 h6/pb6 top view pin-out and package motorola DSP56156 data sheet 53 figure 40 bottom view of the DSP56156 112-pin plastic (fc) and ceramic (fe) quad flat packages note: an overbar indicates the signal is asserted when the voltage = ground (active low). moda/irqa reset std0/pc0 srd0/pc1 sck0/pc2 sc10/pc3 sc00/pc4 tin/pc10 v cc7 tout/pc11 ha0/pb8 gnd10 ha1/pb9 ha2/pb10 hr/w /pb11 hen /pb12 hack /pb14 hreq /pb13 h0/pb0 h1/pb1 std1/pc5 srd1/pc6 h4/pb4 h3/pb3 h2/pb2 v cc6 h5/pb5 h6/pb6 gnd4 d2 d3 v cc3 d4 d5 gnd5 d6 d7 d8 d9 gnd6 d10 d11 v cc4 d12 d13 gnd7 d14 d15 ta dr v cca spkp spkm gnda vdiv vref orientation mark 1 29 57 85 h7/pb7 sck1/pc7 sc11/pc8 gnd9 sc01/pc9 extal v ccs sxfc gnds gndq0 clko dsi/os0 dsck/os1 dso r/w bs ps/ds rd gnd8 wr v cc5 bb br v ccq0 bg bias aux mic modb/irqb modc a0 a1 gnd0 a2 a3 v cc1 a4 a5 gnd1 v ccq1 a6 a7 a8 a9 gnd2 a10 v cc2 gndq1 a11 a12 a13 gnd3 a14 a15 d0 d1 (on top side) (bottom view) bottom view pin-out and package 54 DSP56156 data sheet motorola table 23 DSP56156 general purpose i/o pin identification 112-pin package pin # DSP56156 primary pin function DSP56156 general purpose i/o id 66 h0 pb0 65 h1 pb1 60 h2 pb2 61 h3 pb3 62 h4 pb4 58 h5 pb5 57 h6 pb6 56 h7 pb7 74 ha0 pb8 72 ha1 pb9 71 ha2 pb10 70 hr/w pb11 69 hen pb12 67 hreq pb13 68 hack pb14 82 std0 pc0 81 srd0 pc1 80 sck0 pc2 79 sc10 pc3 78 sc00 pc4 64 std1 pc5 63 srd1 pc6 55 sck1 pc7 54 sc11 pc8 52 sc01 pc9 77 tin pc10 75 tout pc11 general purpose i/o notes: 1. in tables 23, 24, and 25, overbar indicates the signal is asserted when the voltage = ground (active low). 2. for more information on power and ground, see table 26 under design considerations. pin-out and package motorola DSP56156 data sheet 55 pin number pin-out and package 56 DSP56156 data sheet motorola table 24 DSP56156 pin identification by pin number 112-pin package pin # signal name 112-pin package pin # signal name 112-pin package pin # signal name 1gnd4 39rd 76 v cc7 2d2 40ps/ds 77 tin/pc10 3d3 41bs 78 sc00/pc4 4v cc3 42 r/w 79 sc10/pc3 5 d4 43 dso 80 sck0/pc2 6 d5 44 dsck/os1 81 srd0/pc1 7 gnd5 45 dsi/os0 82 std0/pc0 8d6 46clko 83reset 9d7 47gndq0 84moda/irqa 10 d8 48 gnds 85 modb/irqb 11 d9 49 sxfc 86 modc 12 gnd6 50 v ccs 87 a0 13 d10 51 extal 88 a1 14 d11 52 sc01/pc9 89 gnd0 15 v cc4 53 gnd9 90 a2 16 d12 54 sc11/pc8 91 a3 17 d13 55 sck1/pc7 92 v cc1 18 gnd7 56 h7/pb7 93 a4 19 d14 57 h6/pb6 94 a5 20 d15 58 h5/pb5 95 gnd1 21 ta 59 v cc6 96 v ccq1 22 dr 60 h2/pb2 97 a6 23 v cca 61 h3/pb3 98 a7 24 spkp 62 h4/pb4 99 a8 25 spkm 63 srd1/pc6 100 a9 26 gnda 64 std1/pc5 101 gnd2 27 vdiv 65 h1/pb1 102 a10 28 vref 66 h0/pb0 103 v cc2 29 mic 67 hreq /pb13 104 gndq1 30 aux 68 hack /pb14 105 a11 31 bias 69 hen /pb12 106 a12 32 bg 70 hr/w /pb11 107 a13 33 v ccq0 71 ha2/pb10 108 gnd3 34 br 72 ha1/pb9 109 a14 35 bb 73 gnd10 110 a15 36 v cc5 74 ha0/pb8 111 d0 37 wr 75 tout/pc11 112 d1 38 gnd8 signal name pin-out and package motorola DSP56156 data sheet 57 signal name pin-out and package 58 DSP56156 data sheet motorola table 25 DSP56156 pin identification by signal name 112-pin package pin # signal name 112-pin package pin # signal name 112-pin package pin # signal name 87a0 6d5 47gndq0 88 a1 8 d6 104 gndq1 90a2 9d7 48gnds 91 a3 10 d8 66 h0 93 a4 11 d9 65 h1 94 a5 13 d10 60 h2 97 a6 14 d11 61 h3 98 a7 16 d12 62 h4 99 a8 17 d13 58 h5 100 a9 19 d14 57 h6 102 a10 20 d15 56 h7 105 a11 22 dr 74 ha0 106 a12 44 dsck 72 ha1 107 a13 45 dsi 71 ha2 109 a14 43 dso 68 hack 110 a15 51 extal 69 hen 30 aux 89 gnd0 70 hr/w 35 bb 95 gnd1 67 hreq 32 bg 101 gnd2 84 irqa 31 bias 108 gnd3 85 irqb 34 br 1 gnd4 29 mic 41 bs 7 gnd5 84 moda 46 clko 12 gnd6 85 modb 111 d0 18 gnd7 86 modc 112d1 38gnd8 45os0 2d2 53gnd9 44os1 3d3 73gnd10 66pb0 5d4 26gnda 65pb1 pin-out and package motorola DSP56156 data sheet 59 pin-out and package 60 DSP56156 data sheet motorola table 25 DSP56156 pin identification by signal name (continued) 112-pin package pin # signal name 112-pin package pin # signal name 112-pin package pin # signal name 60 pb2 55 pc7 64 std1 61 pb3 54 pc8 49 sxfc 62 pb4 52 pc9 21 ta 58pb5 77pc10 77tin 57pb6 75pc11 75tout 56 pb7 40 ps/ds 92 v cc1 74 pb8 42 r/w 103 v cc2 72 pb9 39 rd 4v cc3 71 pb10 83 reset 15 v cc4 70 pb11 78 sc00 36 v cc5 69 pb12 52 sc01 59 v cc6 67 pb13 79 sc10 76 v cc7 68 pb14 54 sc11 23 v cca 82pc0 80sck0 33v ccq0 81pc1 55sck1 96v ccq1 80pc2 25spkm 50v ccs 79pc3 24spkp 27vdiv 78 pc4 81 srd0 28 vref 64 pc5 63 srd1 37 wr 63 pc6 82 std0 pin-out and package motorola DSP56156 data sheet 61 112 cqfp pin-out and package 62 DSP56156 data sheet motorola -l- view y pin 1 identifier 112 1 28 29 56 57 84 85 ce w g 108 place view p 0.15 (0.006) 0.20 (0.008) t l-m s n s m 0.20 (0.008) tl-m s n s m 0.20 (0.008) tl-m n 0.20 (0.008) tl-m n a s -m- b v -n- -h- datum plane -t- seating plane j1 j1 p view y 3 place -l-, -m-, -n- a1 q 1 q 2 r r1 r r2 k -h- datum plane view p c1 min min max max millimeters inches dim a b c d e f g j k p s v w a1 b1 c1 r1 r2 q 2 18.880 18.880 2.740 0.220 2.340 0.220 0.130 0.650 22.950 22.950 0.300 0.200 0.120 0 20.400 20.400 3.450 0.380 3.060 0.330 0.230 0.950 23.450 23.450 0.600 0.132 0.743 0.743 0.108 0.009 0.092 0.009 0.005 0.026 0.904 0.904 0.012 0.008 0.0047 0.803 0.803 0.135 0.015 0.120 0.013 0.009 0.037 0.923 0.923 0.024 0.0052 0.650 bsc 0.0256 bsc 0.325 bsc 0.0128 bsc 1.800 ref 0.070 ref 0.200 ref 0.008 ref 0.200 ref 0.008 ref notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane -h- is coincident with the bottom of the lead where the lead exits the ceramic body. 4. datums -l-, -m- and -n- to be determined at datum plane -h-. 5. dimensions s and v to be determined at seating plane -t-. 6. dimensions a and b define maximum ceramic body dimensions including glass protrusion and mismatch. q 1 0 8 8 0 0 8 8 m 0.127 (0.005) t l-m n base metal plating section j1-j1 112 place view rotated 90 f d j b1 figure 41 DSP56156 112-pin ceramic quad flat pack (cqfp) mechanical information s s m m s s s s note: bsc = between statistical center (i.e., typical) top view case 915-01 pin-out and package motorola DSP56156 data sheet 63 112 tqfp pin-out and package 64 DSP56156 data sheet motorola 0.100 (0.004) c c2 view ab seating plane -t- -l-, -m-, -n- view y j1 j1 f j d base metal aa section j1-j1 (view rotated 90 counter clockwise) view ab q 1 r2 r1 0.13 (0.005) t l -m m c m m view y dim min max min max inches millimeters a 20.000 bsc 0.790 bsc a1 10.000 bsc 0.395 bsc b 20.000 bsc 0.790 bsc b1 10.000 bsc 0.395 bsc c 1.400 1.600 0.055 0.063 c1 0.050 0.150 0.002 0.006 c2 1.350 1.450 0.053 0.057 d 0.270 0.370 0.011 0.014 e 0.450 0.750 0.018 0.030 f 0.270 0.330 0.011 0.013 g 0.650 bsc 0.0256 bsc j 0.115 0.175 0.006 0.007 k 0.500 bsc 0.020 bsc p 0.325 bsc 0.013 bsc r1 0.100 0.200 0.004 0.008 r2 0.100 0.200 0.004 0.008 s 22.000 bsc 0.866 bsc s1 11.000 bsc 0.433 bsc v 22.000 bsc 0.866 bsc v1 11.000 bsc 0.433 bsc y 0.250 ref 0.010 ref z 1.000 ref 0.039 ref aa 0.115 0.135 0.004 0.005 q q 1 q 2 q 3 pin 1 identifier 112 85 84 56 28 57 1 29 -l- -m- -n- v1 s1 0 3 11 11 0 3 11 11 8 7 13 13 8 7 13 13 0.200 (0.008) t l-m n 0.200 (0.008) h l-m n 4x 4x 28 tips q 3 q 2 s a v b b1 a1 q c1 0.25 (0.010) 4x p 108x g gage plane 0.050 (0.002) s -h- y k e z notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane -h- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums -l-, -m- and -n- to be determined at datum plane -h-. 5. dimensions s and v to be determined at seating plane -t-. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane -h-. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall not cause the d dimension to exceed 0.43 (0.017). figure 42 DSP56156 112-pin plastic thin quad flat pack (tqfp) mechanical information note: bsc = between statistical center (i.e., typical) top view case 987-01 design considerations 60 DSP56156 data sheet motorola design considerations q jc is device-related and cannot be influ- enced by the user. however, q ca is user-de- pendent and can be minimized by such thermal management techniques as heat sinks, ambient air cooling, and thermal con- vection. thus, good thermal management on the part of the user can significantly reduce q ca so that q ja approximately equals q jc . substitution of q jc for q ja in equation (1) will result in a lower semiconductor junction temperature. values for thermal resistance presented in this document, unless estimat- ed, were derived using the procedure de- scribed in motorola reliability report 7843, thermal resistance measurement method for mc68xx microcomponent devices, and are provided for design purposes only. ther- mal measurements are complex and depen- dent on procedure and setup. user-derived values for thermal resistance may differ. power, ground, and noise each DSP56156 v cc pin should be provided with a low-impedance path to +5 volts. each DSP56156 gnd pin should likewise be pro- vided with a low-impedance path to ground. the power supply pins drive distinct groups of logic on chip as shown in table 26. the v cc power supply should be by- passed to gnd ground using at least six 0.01 C 0.1 f bypass capacitors located ei- ther underneath the chips socket or as close as possible to the four sides of the package. the capacitor leads and the associated printed circuit traces connecting to chip v cc and gnd should be kept to less than 0.5 per heat dissipation the average chip junction temperature, t j , in c, can be obtained from: t j = t a + (p d q ja )(1) where: t a = ambient temperature, c q ja = package thermal resistance, junction-to-ambient, c/w p d =p int + p i/o p int =i cc v cc watts chip internal power p i/o = power dissipation on input and output pins user determined for most applications p i/o < p int and p i/o can be neglected. an appropriate relationship be- tween p d and t j (if p i/o is neglected) is: p d = k/(t j + 273) (2) solving equations (1) and (2) for k gives: k = p d (t a + 273) + p d q ja (3) where k is a constant pertaining to the partic- ular package. k can be determined from equation (2) by measuring p d (at equilibri- um) for a known t a . using this value of k, the values of p d and t j can be obtained by solv- ing equations (1) and (2) iteratively for any value of t a . the total thermal resistance of a package ( q ja ) can be separated into two com- ponents, q jc and q ca , representing the barrier to heat flow from the semiconductor junction to the package (case) surface ( q jc ) and from the case to the outside ambient ( q ca ). these terms are related by the equation: q ja = q jc + q ca (4) heat dissipation power, ground, and noise design considerations motorola DSP56156 data sheet 61 capacitor lead. the use of at least a four lay- er board is recommended, employing two inner layers as v cc and gnd planes. all output pins on this dsp have fast rise and fall times. printed circuit board (pcb) trace length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times. this recommendation particularly applies to the address and data buses as well as the ps/ds , bs , rd , wr , r/w , inter- rupt, and hen pins. maximum pcb trace lengths on the order of 6" are recommended. capacitance calculations should consider all device loads as well as parasitic capacitanc- es due to pcb traces. attention to proper pcb layout and bypassing becomes espe- cially critical in systems with higher capac- itive loads because these loads create higher transient currents in the v cc and gnd circuits. clock signals should not be run across many signals and should be kept away from analog power and ground traces as well as any analog signals. see figure 44 for more details. power, ground, and noise table 26 power and ground connections circuitry power ground signal name pin # signal name pin # address bus buffers v cc1 v cc2 92 103 gnd0 gnd1 gnd2 gnd3 89 95 101 108 data bus buffers v cc3 v cc4 4 15 gnd4 gnd5 gnd6 gnd7 1 7 12 18 bus control buffers v cc5 36 gnd8 38 codec v cca 23 gnda 26 digital peripherals v cc6 v cc7 59 76 gnd9 gnd10 53 73 internal logic v ccq0 v ccq1 33 96 gndq0 gndq1 47 104 phase-locked loop (pll) v ccs 50 gnds 48 design considerations 62 DSP56156 data sheet motorola power consumption (v cc = 5.0 v dc 10%, t j = -40 to +125 c, c l = 50 pf + 1 ttl load) the dc electrical characteristics of this device are shown in table 27. power consumption is application dependant. the data in table 27 is collected by running the following code using internal memory after having programmed all pins of port b and c as input and after having three-stated the data bus (mc = 0 in omr) and pulled high: move #0,r0 move #0,r3 move #$100,r2 move #$00ff,m0 loop clr a move x:(r0)+,a ;initial value to accumulator move a1,a0 rep #30 mac x0,y0,a x:(r3)+,x0 ;mac on typical data move a,p:(r2) ;store the mac result move #0,r3 jmp loop to minimize the power dissipation, all unused digital input pins should be tied inactive to ground or power; and all unused i/o pins should be tied inactive through a 10k? resistor to ground or power. when the codec is not used, gnda should be connected to gnd; and v cca should be connected to v cc . also, all codec pins should be left floating, except vref which should still be decoupled. table 27 dc electrical characteristics conditions symbol typical unit 40 mhz 50 mhz 60 mhz digital current with codec and pll disabled i cc 91 112 133 ma digital current wait mode with codec and pll disabled i cc 12 14 17 ma digital current wait mode with codec enabled and pll disabled i cc 92 113 134 ma stop mode with pll and clko disabled i cc 250 a digital current drawn by the pll when active i cc 1ma digital current drawn by clko when active i cc 3.6ma analog current with codec enabled i cca 12ma analog current with codec disabled i cca 70a power consumption design considerations motorola DSP56156 data sheet 63 host port considerations careful synchronization is required when reading multi-bit registers that are written by another asynchronous system. this is a com- mon problem when two asynchronous sys- tems are connected. the situation exists in the host interface. the considerations for proper operation are discussed below. host programming considerations 1. unsynchronized reading of receive byte registers when reading receive byte registers, rxh or rxl, the host program should use interrupts or poll the rxdf flag which indicates that data is available. this assures that the data in the receive byte registers will be stable. 2. overwriting transmit byte registers the host program should not write to the transmit byte registers, txh or txl, un- less the txde bit is set indicating that the transmit byte registers are empty. this guarantees that the transmit byte regis- ters will transfer valid data to the hrx register. 3. synchronization of status bits from dsp to host hc, hreq, dma, hf3, hf2, trdy, txde, and rxdf status bits are set or cleared from inside the dsp and read by the host processor (refer to DSP56156 us- ers manual , i/o interface section, host/ dma interface programming model for descriptions of these status bits). the host can read these status bits very quick- ly without regard to the clock rate used by the dsp, but the possibility exists that the state of the bit could be changing dur- ing the read operation. this is generally not a system problem, since the bit will be read correctly in the next pass of any host polling routine. however, if the host asserts hen for more than timing number 101 (t101), with a minimum cycle time of timing number 103 (t103), then these status bits are guaranteed to be stable. care must be exercised when reading status bits hf3 and hf2 as an encoded pair. if the dsp changes hf3 and hf2 from 00 to 11, there is a small probability that the host could read the bits during the transition and receive 01 or 10 instead of 11. if the combination of hf3 and hf2 has signif- icance, the host could read the wrong combination. therefore, read the bits twice and check for consensus. 4. overwriting the host vector the host program should change the host vector register only when the host command bit (hc) is clear. this change will guarantee that the dsp interrupt control logic will receive a stable vector. 5. cancelling a pending host command exception the host processor may elect to clear the hc bit to cancel the host command ex- ception request at any time before it is recognized by the dsp. because the host does not know exactly when the excep- tion will be recognized (due to exception processing synchronization and pipeline delays), the dsp may execute the host command exception after the hc bit is cleared. for these reasons, the hv bits must not be changed at the same time that the hc bit is cleared. host port considerations design considerations 64 DSP56156 data sheet motorola dsp programming considerations 1. synchronization of status bits from host to dsp dma, hf1, hf0, and hcp, htde, and hrdf status bits are set or cleared by the host processor side of the interface. these bits are individ- ually synchronized to the dsp clock. (refer to the DSP56156 users manual , i/o interface section, host/dma in- terface programming model for de- scriptions of these status bits.) 2. reading hf0 and hf1 as an encoded pair care must be exercised when reading status bits hf0 and hf1 as an encod- ed pair, i.e., the four combinations 00, 01, 10, and 11 each have significance. a very small probability exists that the dsp will read the status bits syn- chronized during transition. there- fore, hf0 and hf1 should be read twice and checked for consensus. bus operation figure 43 depicts the operation of the external memory interface with multiple wait states. figure 43 read and write bus operation (3 wait states) t0 t1 t2 tw t2 tw t2 tw t2 t3 t0 t1 t2 tw t2 tw t2 tw t2 t3 t0 t1 t data out clko bs a0-a15 ps/ds r/w wr rd d0-d15 data in dsp programming considerations bus operation design considerations motorola DSP56156 data sheet 65 analog i/o considerations figure 44 describes the recommended analog i/o and power supply configurations. the two analog inputs are electrically identical. when one is not used, it can be left floating. when used, an ac coupling capacitor is required. the value of the capacitor along with the input impedance of the pin determine the cut off frequency of a high pass filter. the input imped- ance of the mic and aux varies as a function of the sigma-delta (2y) modulator master clock. 78 k w is a typical value at 2 mhz. an ac capacitor of 1f defines a high pass filter pole of 2 hz. a smaller capacitor value will move this pole higher in frequency. figure 44 recommended analog i/o configuration sd modulator 2.0 v 10% ( 1ma) mic vref aux bias ?10 m f -6 db 6 db mgs1-0 bits 3 pole 2 zero low pass filter (lpf) vc3-vc0 (to microphone) spkp (2/5 v cc ) + digital v cc ins bit 17 db vdiv e50 nf 1 m f 600 w 0.001 m f 1 m f 600 w r bias 15 m f 0.1 m f +5 db 54 k w 36 k w ?1 k w 10 k w 5.6 k w vref 0.001 m f v cca gnda + 15 m f 0.1 m f mux gnda gnda +5 v + 220 m f analog decoupling near dsp single trace external external supply gnd digital gnd single trace gnda v cca 0.01 m f spkm 5.6 k w vref gnd analog i/o considerations design considerations 66 DSP56156 data sheet motorola figure 45 shows three possible single-ended output configurations. configuration (a) is highly recommended. for configurations (b) and (c), an ac coupling capacitor is required since the load resistor is tied to gnda. figure 46 shows a recommended layout for power and ground planes. figure 46 ground and power planes ? 500 w spkp spkm ? 500 w 47 k? 47 k? 47 k? vref 47 k ? spkp spkm spkp spkm ? 500 w 0 < c e 100 nf nc (a) (b) (c) - + v cca gnda 0 < c e 100 nf 0 < c e 100 nf figure 45 single-ended output configurations 128 84 57 56 29 112 85 analog ground and power planes digital ground and power planes analog i/o considerations design considerations motorola DSP56156 data sheet 67 a four level board is recommended. the top layer (directly under the parts) and the bottom layer should be interconnect layers. the two center layers should be power and ground. ground and power planes should be completely separated. the digital and analog power/ ground planes should not overlap. all codec pins should be over the analog planes. the ana- log planes should not encompass any digital pins. all codec signal traces should be over the analog planes. figure 47 shows that 0.1 m f bypass caps should be located as close to the pins being bypassed as possible. the ground side of these caps should be connected as close as possible to the v cca pin. the ground side of the bypass cap should be connected to the v cca pin by short traces. figure 47 suggested top layer bypassing the pins with 0.1 m f bypass caps are vref and gnda. the largest size practical bypass caps should also be added for each of these pins as well as for the vdiv pin; 10 m f bypass caps should be considered a minimum value for the larger caps (65 m f on vdiv may be used). these caps should be near the package but do not have to be right next to the pins. the dac outputs (spkp and spkm) should be run right next to each other as shown on figure 48. 28 29 gnda spkp spkm v cca bias aux mic 0.1 m f 0.1 m f ?10 f 25 m f vdiv vref 65 m f 10 k w analog i/o considerations design considerations 68 DSP56156 data sheet motorola figure 48 suggested bottom layer routing the output should be used differentially if at all possible. analog signal traces should be shielded by running traces connected to analog ground next to them. unused board area on both interconnect levels should be copper filled and connected to analog ground. the copper fill is only shown on this page for clarity and simplicity. the adc input anti-aliasing should be done with respect to vref. figure 49 presents four options for good power supply connections. 28 29 gnda spkp spkm v cca 0.25 m f 47 k w 47 k w copper fill of unused board space should be connected to the analog ground plane. bias aux mic vdiv vref 47 k w 1nf 47 k w 5.6 k w mic in spk out analog i/o considerations design considerations motorola DSP56156 data sheet 69 figure 49 four possible power supply connections 28 29 gnda spkp spkm v cca aux mic vref vdiv ideal choice two separate power supplies. ground planes connected with a single trace as close as possible to the v cca pin on the codec. gnda spkp spkm v cca second choice one power supply. two regulators, one for the digital supply, one for the analog supply. ground planes connected with a 10 ? resistor as close as possible to the v cca pin on the codec. 10 w voltage regulator bias 28 29 aux mic vref vdiv bias voltage regulator third choice one power supply. one regulator for the analog supply. digital sup- plies driven directly by voltage source. ground planes connected with a 10 ? resistor as close as possible to the v cca pin on the codec. 10 w fourth choice one power supply. ground planes connected at source. ground planes connected with a 10 ? resistor as close as pos- sible to the v cca pin on the codec. 28 29 gnda spkp spkm v cca aux mic vref vdiv bias 10 w 28 29 gnda spkp spkm v cca aux mic vref vdiv bias voltage regulator analog i/o considerations ordering information 70 DSP56156 data sheet motorola ordering information table 28 lists information for ordering parts. table 28 DSP56156 ordering information supply voltage package type pin count frequency (mhz) order number 5 v ceramic quad flat pack (cqfp) 112 40 DSP56156fe40 60 DSP56156fe60 5 v plastic thin quad flat pack (tqfp) 112 40 DSP56156fv40 60 DSP56156fv60 motorola motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or d esign. motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any lice nse under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical i mplant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product cou ld create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damag es, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and m are registered trademarks o f motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. literature distribution centers: usa: motorola literature distribution; p.o. box 20912; phoenix, arizona 85036. europe: motorola ltd.; european literature center; 88 tanners drive, blakelands, milton keynes, mk14 5bp, england. japan: nippon motorola ltd.; 4-32-1, nishi-gotanda, shinagawa-ku, tokyo 141 japan. asia-pacific: motorola semiconductors h.k. ltd.; silicon harbor center, no. 2 dai king street, tai po industrial estate, tai po , n.t., hong kong. |
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